Showing posts with label Electronics Notes. Show all posts
Showing posts with label Electronics Notes. Show all posts
Thursday, August 27, 2009
BIT FOR INTELLIGENT SYSTEM DESIGN
The increasing complexity of microelectronic circuitry, as witnessed by multi-chip modules and system-on-a-chip and the rapid growth of manufacturing process automation require, that more effective and efficient testing and fault diagnosis techniques be developed to improve system reliability, reduce system downtime, and esemnhance productivity. As a design philosophy, built-in-test (BIT) is receiving increasing attention from the research community. This paper presents an overview of BIT search in several areas of industry, including semiconductor, manufacturing.
Friday, August 14, 2009
Block Oriented Instrument Software Design
Block Oriented Instrument Software Design
A new method for writing instrumentation software is proposed. It is based on the abstract description of the instrument operation and combines the advantages of a reconfigurable instrument and interchangeability of the instrumentation modules. The proposed test case is the implementation of a microwave network analyzer for nonlinear systems based on VISA and plug and play instrument drivers.
Modern Instruments or Instrumentation setups are likely to be built-up around generic hardware and custom software. The disadvantage is that the amount of software required to operate such a device is very high. An acceptable development time for a reasonably low number of software bugs can therefore only be obtained if the software is maximally reused from earlier developments. Most attempts used a two-step approach. In the first step transport interface between computer and instrument is abstracted. The first step in this approach has always been quite successful. The first transport abstraction stems from the IEEE-488 interface. Afterward SICL and VISA were developed to support multiple transport busses (IEEE-488, RS-232 and later Ethernet and IEE-1394). These methods use a file as the conceptual model for an instrument. The commands sent to the files are independent of the transmission medium, medium dependency is localized only in the initialization call. Most interfaces that can be used for instrumentation control are, hence, supported by these frameworks.
In the second step the instrumentation command is abstracted to empower interchangeability of similar pieces of instrumentation. For this, the situation always has been much less obvious. Only end-users have something to gain in instrument interchangeability. An abstract model to programming instrumentation setups is proposed which is easy and general enough to be used for complex setups.
INTELLIGENT SYSTEM DESIGN
INTELLIGENT SYSTEM DESIGN
The increasing complexity of microelectronic circuitry, as witnessed by multi-chip modules and system-on-a-chip and the rapid growth of manufacturing process automation require, that more effective and efficient testing and fault diagnosis techniques be developed to improve system reliability, reduce system downtime, and esemnhance productivity. As a design philosophy, built-in-test (BIT) is receiving increasing attention from the research community. This paper presents an overview of BIT search in several areas of industry, including semiconductor, manufacturing.
The increasing complexity of microelectronic circuitry, as witnessed by multi-chip modules and system-on-a-chip and the rapid growth of manufacturing process automation require, that more effective and efficient testing and fault diagnosis techniques be developed to improve system reliability, reduce system downtime, and esemnhance productivity. As a design philosophy, built-in-test (BIT) is receiving increasing attention from the research community. This paper presents an overview of BIT search in several areas of industry, including semiconductor, manufacturing.
Tuesday, August 11, 2009
Asynchronous circuit
Asynchronous circuit
An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signals.
Theoretical foundations
Petri Nets are an attractive and powerful model for reasoning about asynchronous circuits. However Petri nets have been criticized by Carl Hewitt for their lack of physical realism (see Petri net#Subsequent models of concurrency). Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model and process calculi.
The term asynchronous logic is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model - which uses 'conventional' data processing elements with completion indicated by a locally generated delay model - to delay-insensitive design - where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger and slower than synchronous (or bundled data) implementations, but which are insensitive to layout and parametric variations and are thus "correct by design."
Benefits
Different classes of asynchronous circuitry offer different advantages. Below is a list of the advantages offered by Quasi Delay Insensitive Circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:
* Robust handling of metastability of arbiters.* Early Completion of a circuit when it is known that the inputs which have not yet arrived are irrelevant.* Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gating in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, which can result in increased power consumption if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of high-K dielectrics).* Freedom from the ever-worsening difficulties of distributing a high-fanout, timing-sensitive clock signal.* Better modularity and composability.* Far fewer assumptions about the manufacturing process are required (most assumptions are timing assumptions).* Circuit speed is adapted on the fly to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.* Immunity to transistor-to-transistor variability in the manufacturing process, which is one of the most serious problems facing the semiconductor industry as dies shrink.* Less severe electromagnetic interference. Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.* In asynchronous circuits, local signaling eliminates the need for global synchronization which exploits some potential advantages in comparison with synchronous ones. They have shown potential specifications in low power consumption, design reuse, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations.
Disadvantages
* Increased Complexity* More Difficult to Design* the performance analysis of asynchronous circuits is a complicated problem
Applications
Asynchronous CPU
Asynchronous CPUs are one of several ideas for radically changing CPU design.
Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline. Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:
* components can run at different speeds on an asynchronous CPU; all major components of a clocked CPU must remain synchronized with the central clock;* a traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. When an asynchronous CPU completes an operation more quickly than anticipated, the next stage can immediately begin processing the results, rather than waiting for synchronization with a central clock. An operation might finish faster than normal because of attributes of the data being processed (e.g., multiplication can be very fast when multiplying by 0 or 1, even when running code produced by a naive compiler), or because of the presence of a higher voltage or bus speed setting, or a lower ambient temperature, than 'normal' or expected.
Asynchronous logic proponents believe these capabilities would have these benefits:
* lower power dissipation for a given performance level, and* highest possible execution speeds.
The biggest disadvantage of the clockless CPU is that most CPU design tools assume a clocked CPU (i.e., a synchronous circuit). Many tools "enforce synchronous design practices". Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable problems. The group that designed the aforementioned AMULET, for example, developed a tool called LARD to cope with the complex design of AMULET3.
Despite the difficulty of doing so, numerous asynchronous CPUs have been built, including:
* the ORDVAC (?) and the (identical) ILLIAC I (1951), * the ILLIAC II (1962);* The Caltech Asynchronous Microprocessor, the world-first asynchronous microprocessor (1988);* the ARM-implementing AMULET (1993 and 2000);* the asynchronous implementation of MIPS R3000, dubbed MiniMIPS (1998);* the SEAforth multi-core processor (2008) from Charles H. Moore.
The ILLIAC II was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computing machine known to man at the time.
DEC PDP-16 Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.
The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate -- again, with no additional configuration.
An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signals.
Theoretical foundations
Petri Nets are an attractive and powerful model for reasoning about asynchronous circuits. However Petri nets have been criticized by Carl Hewitt for their lack of physical realism (see Petri net#Subsequent models of concurrency). Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model and process calculi.
The term asynchronous logic is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model - which uses 'conventional' data processing elements with completion indicated by a locally generated delay model - to delay-insensitive design - where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger and slower than synchronous (or bundled data) implementations, but which are insensitive to layout and parametric variations and are thus "correct by design."
Benefits
Different classes of asynchronous circuitry offer different advantages. Below is a list of the advantages offered by Quasi Delay Insensitive Circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:
* Robust handling of metastability of arbiters.* Early Completion of a circuit when it is known that the inputs which have not yet arrived are irrelevant.* Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gating in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, which can result in increased power consumption if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of high-K dielectrics).* Freedom from the ever-worsening difficulties of distributing a high-fanout, timing-sensitive clock signal.* Better modularity and composability.* Far fewer assumptions about the manufacturing process are required (most assumptions are timing assumptions).* Circuit speed is adapted on the fly to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.* Immunity to transistor-to-transistor variability in the manufacturing process, which is one of the most serious problems facing the semiconductor industry as dies shrink.* Less severe electromagnetic interference. Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.* In asynchronous circuits, local signaling eliminates the need for global synchronization which exploits some potential advantages in comparison with synchronous ones. They have shown potential specifications in low power consumption, design reuse, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations.
Disadvantages
* Increased Complexity* More Difficult to Design* the performance analysis of asynchronous circuits is a complicated problem
Applications
Asynchronous CPU
Asynchronous CPUs are one of several ideas for radically changing CPU design.
Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline. Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:
* components can run at different speeds on an asynchronous CPU; all major components of a clocked CPU must remain synchronized with the central clock;* a traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. When an asynchronous CPU completes an operation more quickly than anticipated, the next stage can immediately begin processing the results, rather than waiting for synchronization with a central clock. An operation might finish faster than normal because of attributes of the data being processed (e.g., multiplication can be very fast when multiplying by 0 or 1, even when running code produced by a naive compiler), or because of the presence of a higher voltage or bus speed setting, or a lower ambient temperature, than 'normal' or expected.
Asynchronous logic proponents believe these capabilities would have these benefits:
* lower power dissipation for a given performance level, and* highest possible execution speeds.
The biggest disadvantage of the clockless CPU is that most CPU design tools assume a clocked CPU (i.e., a synchronous circuit). Many tools "enforce synchronous design practices". Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable problems. The group that designed the aforementioned AMULET, for example, developed a tool called LARD to cope with the complex design of AMULET3.
Despite the difficulty of doing so, numerous asynchronous CPUs have been built, including:
* the ORDVAC (?) and the (identical) ILLIAC I (1951), * the ILLIAC II (1962);* The Caltech Asynchronous Microprocessor, the world-first asynchronous microprocessor (1988);* the ARM-implementing AMULET (1993 and 2000);* the asynchronous implementation of MIPS R3000, dubbed MiniMIPS (1998);* the SEAforth multi-core processor (2008) from Charles H. Moore.
The ILLIAC II was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computing machine known to man at the time.
DEC PDP-16 Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.
The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate -- again, with no additional configuration.
INFORMATION SEARCH, ANALYSIS AND PRESENTATION (ISAP)
INFORMATION SEARCH, ANALYSIS AND PRESENTATION (ISAP)
One of the primary focuses of technical education is to produce employable graduates/technicians. Through a sound knowledge of the subjects is impact. ISAP play a vital role in employability. Graduates/technicians without a good communication would not be able to face a placement committee ISAP is necessary not only in placement but also for job success.
For candidates who are entering into the carriers for the first time. The following skills are highly recommended and they must be trained in the following areas:
1. Communication Skill.2. Presentation Skill.3. Writing Skill.4. Group Discussion.5. Case Study.6. Preparing job hunting material.7. Resume preparation.8. Facing the interview.9. Carrier exploration10. Use of communication technologies.
Barriers to Communication
There are number of barriers to communication which produce noise and prevent the achievement of desired result some of these are:
1. Badly encoded message.2. Disturbance in the transmission channel.3. Poor retention.4. Inattention by the receiver.5. Unclassified assumption.6. Mistrust between sender and receiver.7. Premature evaluation of the message.8. Differences in perception.9. Misinterpretation of the message.10. Selection of wrong variety of long wage.
Classification of Communication
1. Non-verbal communication2. Verbal communication
Non-Verbal communication:
Non-Verbal communication refers to all external stimuli other than spoken or written words and including body motion. Characteristics of appearance,characteristics of voice and use of space and distancing.
All these non-verbal clues taken together are also known as body language.
Verbal Communication:
Verbal Communication includes oral communication and written communication.Body language plays a significant role in oral communication in day-to-day oral communication we kept on interpreting non verbal clues without being aware that we doing so.
Definition
It is defined as documented prose work incorporating the result of an organised analysis of a subject. In its style structure and approach closely resembles a formal report. But in certain respects research papers differ from a formal report is always prompted by a specific need of the organisation.
Research paper and Articles:
Characteristics feature of a research paper are:-1. A research paper may be written about any subject social, cultural, scientific and technical, etc., But the treatment is scholarly and is supported by evidence.2. There is a relatively high concentration of a certain writing techniques such as a definitions, classification interpretation and description of a process.3. Its formal elements are generally those of a report and the writing is characterised by the use of graph cards and scientific technical or specialised vocabulary.4. The emphasis is an presentation of information accurately and concisely and the writer maintains an attitude of complete impartiality and objectivity.
Types
There are three types of research paper1. Library research paper of a term. Paper or a theme paper.2. Scientific paper.3. Technical paper
Library Research Paper:
There are three preparatory steps in writing such a paper namely.1. Selecting a subject.2. Locating a source of information3. Note marking
Usually such a paper is written under the guidance of an instructor and the student is advised how to go about it.
The scientific paper and technical paper are often used interchangeably to refer to a research paper. When a distinction is made it is on the basic of its contents
One of the primary focuses of technical education is to produce employable graduates/technicians. Through a sound knowledge of the subjects is impact. ISAP play a vital role in employability. Graduates/technicians without a good communication would not be able to face a placement committee ISAP is necessary not only in placement but also for job success.
For candidates who are entering into the carriers for the first time. The following skills are highly recommended and they must be trained in the following areas:
1. Communication Skill.2. Presentation Skill.3. Writing Skill.4. Group Discussion.5. Case Study.6. Preparing job hunting material.7. Resume preparation.8. Facing the interview.9. Carrier exploration10. Use of communication technologies.
Barriers to Communication
There are number of barriers to communication which produce noise and prevent the achievement of desired result some of these are:
1. Badly encoded message.2. Disturbance in the transmission channel.3. Poor retention.4. Inattention by the receiver.5. Unclassified assumption.6. Mistrust between sender and receiver.7. Premature evaluation of the message.8. Differences in perception.9. Misinterpretation of the message.10. Selection of wrong variety of long wage.
Classification of Communication
1. Non-verbal communication2. Verbal communication
Non-Verbal communication:
Non-Verbal communication refers to all external stimuli other than spoken or written words and including body motion. Characteristics of appearance,characteristics of voice and use of space and distancing.
All these non-verbal clues taken together are also known as body language.
Verbal Communication:
Verbal Communication includes oral communication and written communication.Body language plays a significant role in oral communication in day-to-day oral communication we kept on interpreting non verbal clues without being aware that we doing so.
Definition
It is defined as documented prose work incorporating the result of an organised analysis of a subject. In its style structure and approach closely resembles a formal report. But in certain respects research papers differ from a formal report is always prompted by a specific need of the organisation.
Research paper and Articles:
Characteristics feature of a research paper are:-1. A research paper may be written about any subject social, cultural, scientific and technical, etc., But the treatment is scholarly and is supported by evidence.2. There is a relatively high concentration of a certain writing techniques such as a definitions, classification interpretation and description of a process.3. Its formal elements are generally those of a report and the writing is characterised by the use of graph cards and scientific technical or specialised vocabulary.4. The emphasis is an presentation of information accurately and concisely and the writer maintains an attitude of complete impartiality and objectivity.
Types
There are three types of research paper1. Library research paper of a term. Paper or a theme paper.2. Scientific paper.3. Technical paper
Library Research Paper:
There are three preparatory steps in writing such a paper namely.1. Selecting a subject.2. Locating a source of information3. Note marking
Usually such a paper is written under the guidance of an instructor and the student is advised how to go about it.
The scientific paper and technical paper are often used interchangeably to refer to a research paper. When a distinction is made it is on the basic of its contents
INFORMATION SEARCH, ANALYSIS AND PRESENTATION (ISAP)
INFORMATION SEARCH, ANALYSIS AND PRESENTATION (ISAP)
One of the primary focuses of technical education is to produce employable graduates/technicians. Through a sound knowledge of the subjects is impact. ISAP play a vital role in employability. Graduates/technicians without a good communication would not be able to face a placement committee ISAP is necessary not only in placement but also for job success.
For candidates who are entering into the carriers for the first time. The following skills are highly recommended and they must be trained in the following areas:
1. Communication Skill.2. Presentation Skill.3. Writing Skill.4. Group Discussion.5. Case Study.6. Preparing job hunting material.7. Resume preparation.8. Facing the interview.9. Carrier exploration10. Use of communication technologies.
Barriers to Communication
There are number of barriers to communication which produce noise and prevent the achievement of desired result some of these are:
1. Badly encoded message.2. Disturbance in the transmission channel.3. Poor retention.4. Inattention by the receiver.5. Unclassified assumption.6. Mistrust between sender and receiver.7. Premature evaluation of the message.8. Differences in perception.9. Misinterpretation of the message.10. Selection of wrong variety of long wage.
Classification of Communication
1. Non-verbal communication2. Verbal communication
Non-Verbal communication:
Non-Verbal communication refers to all external stimuli other than spoken or written words and including body motion. Characteristics of appearance,characteristics of voice and use of space and distancing.
All these non-verbal clues taken together are also known as body language.
Verbal Communication:
Verbal Communication includes oral communication and written communication.Body language plays a significant role in oral communication in day-to-day oral communication we kept on interpreting non verbal clues without being aware that we doing so.
Definition
It is defined as documented prose work incorporating the result of an organised analysis of a subject. In its style structure and approach closely resembles a formal report. But in certain respects research papers differ from a formal report is always prompted by a specific need of the organisation.
Research paper and Articles:
Characteristics feature of a research paper are:-1. A research paper may be written about any subject social, cultural, scientific and technical, etc., But the treatment is scholarly and is supported by evidence.2. There is a relatively high concentration of a certain writing techniques such as a definitions, classification interpretation and description of a process.3. Its formal elements are generally those of a report and the writing is characterised by the use of graph cards and scientific technical or specialised vocabulary.4. The emphasis is an presentation of information accurately and concisely and the writer maintains an attitude of complete impartiality and objectivity.
Types
There are three types of research paper1. Library research paper of a term. Paper or a theme paper.2. Scientific paper.3. Technical paper
Library Research Paper:
There are three preparatory steps in writing such a paper namely.1. Selecting a subject.2. Locating a source of information3. Note marking
Usually such a paper is written under the guidance of an instructor and the student is advised how to go about it.
The scientific paper and technical paper are often used interchangeably to refer to a research paper. When a distinction is made it is on the basic of its contents
One of the primary focuses of technical education is to produce employable graduates/technicians. Through a sound knowledge of the subjects is impact. ISAP play a vital role in employability. Graduates/technicians without a good communication would not be able to face a placement committee ISAP is necessary not only in placement but also for job success.
For candidates who are entering into the carriers for the first time. The following skills are highly recommended and they must be trained in the following areas:
1. Communication Skill.2. Presentation Skill.3. Writing Skill.4. Group Discussion.5. Case Study.6. Preparing job hunting material.7. Resume preparation.8. Facing the interview.9. Carrier exploration10. Use of communication technologies.
Barriers to Communication
There are number of barriers to communication which produce noise and prevent the achievement of desired result some of these are:
1. Badly encoded message.2. Disturbance in the transmission channel.3. Poor retention.4. Inattention by the receiver.5. Unclassified assumption.6. Mistrust between sender and receiver.7. Premature evaluation of the message.8. Differences in perception.9. Misinterpretation of the message.10. Selection of wrong variety of long wage.
Classification of Communication
1. Non-verbal communication2. Verbal communication
Non-Verbal communication:
Non-Verbal communication refers to all external stimuli other than spoken or written words and including body motion. Characteristics of appearance,characteristics of voice and use of space and distancing.
All these non-verbal clues taken together are also known as body language.
Verbal Communication:
Verbal Communication includes oral communication and written communication.Body language plays a significant role in oral communication in day-to-day oral communication we kept on interpreting non verbal clues without being aware that we doing so.
Definition
It is defined as documented prose work incorporating the result of an organised analysis of a subject. In its style structure and approach closely resembles a formal report. But in certain respects research papers differ from a formal report is always prompted by a specific need of the organisation.
Research paper and Articles:
Characteristics feature of a research paper are:-1. A research paper may be written about any subject social, cultural, scientific and technical, etc., But the treatment is scholarly and is supported by evidence.2. There is a relatively high concentration of a certain writing techniques such as a definitions, classification interpretation and description of a process.3. Its formal elements are generally those of a report and the writing is characterised by the use of graph cards and scientific technical or specialised vocabulary.4. The emphasis is an presentation of information accurately and concisely and the writer maintains an attitude of complete impartiality and objectivity.
Types
There are three types of research paper1. Library research paper of a term. Paper or a theme paper.2. Scientific paper.3. Technical paper
Library Research Paper:
There are three preparatory steps in writing such a paper namely.1. Selecting a subject.2. Locating a source of information3. Note marking
Usually such a paper is written under the guidance of an instructor and the student is advised how to go about it.
The scientific paper and technical paper are often used interchangeably to refer to a research paper. When a distinction is made it is on the basic of its contents
Adaptive cruise control System
Adaptive cruise control System
An automotive cruise control system that automatically slows down the car if it is moving too close to the vehicle in front of it. A radar or laser unit located behind the grille determines the speed and distance of the vehicle in front. When the distance is computed to be safe again, the system accelerates the car back to its last speed setting. Also called "active cruise control" and "intelligent cruise control.
Autonomous cruise control is an optional cruise control system appearing on some more upscale vehicles. The system goes under many different trade names according to the manufacture. These systems use either a radar or laser setup allowing the vehicle to slow when approaching another vehicle and accelerate again to the preset speed when traffic allows. ACC technology is widely regarded as a key component of any future generations of smart cars.
Types
Laser-based systems are significantly lower in cost than radar-based systems; however, laser-based ACC systems do not detect and track vehicles well in adverse weather conditions nor do they track extremely dirty (non-reflective) vehicles very well. Laser-based sensors must be exposed, the sensor (a fairly-large black box) is typically found in the lower grille offset to one side of the vehicle.
Radar-based sensors can be hidden behind plastic fascias; however, the fascias may look different from a vehicle without the feature. For example, Mercedes packages the radar behind the upper grille in the center; however, the Mercedes grille on such applications contains a solid plastic panel in front of the radar with painted slats to simulate the slats on the rest of the grille.
Radar-based systems are available on many luxury cars as an option for approx. 1000-3000 USD/euro. Laser-based systems are available on some near luxury and luxury cars as an option for approx. 400-600 USD/euro.
Cooperating systems
Radar-based ACC often feature a Precrash system, which warns the driver and/or provides brake support if there is a high risk of a collision. Also in certain cars it is incorporated with a lane maintaining system which provides power steering assist to reduce steering input burden in corners when the cruise control system is activated.
Examples of vehicles with adaptive cruise control
2005 Acura RLAudi A4 (see a demonstration on YouTube), A5, A6, A8, Q7BMW 7 Series, 5 series, 6 series, 3 series (Active Cruise Control)2004 Cadillac DTS, STS, XLR2007 Chrysler 300C2006 Ford Mondeo, Taurus, S-Max, Galaxy2003 Honda Inspire Accord, LegendHyundai Genesis (Smart Cruise Control, delayed)Infiniti M, Q45,QX56, G35, FX35/45/50 and G371999 Jaguar XK-R, S-Type, XJ, XF2000 Lexus LS430/460 (laser and radar), RX (laser and radar), GS, IS, ES 350, and LX 570Lincoln MKS, MKT1998 Nissan Cima, Nissan Primera T-Spec Models (Intelligent Cruise Control)1998 Mercedes-Benz S-Class, E-Class, CLS-Class, SL-Class, CL-Class, M-Class, GL-Class, CLK-Class (Distronic, removed in 2009 from certain US models)Range Rover SportRenault Vel SatisSubaru Legacy & Outback Japan-spec called SI-Cruise1997 Toyota Celsior, Sienna (XLE Limited Edition), Avalon, Sequoia (Platinum Edition), Prius, AvensisVolkswagen Passat, Phaeton, Touareg, 2009 GolfVolvo S80, V70, XC70, XC60
An automotive cruise control system that automatically slows down the car if it is moving too close to the vehicle in front of it. A radar or laser unit located behind the grille determines the speed and distance of the vehicle in front. When the distance is computed to be safe again, the system accelerates the car back to its last speed setting. Also called "active cruise control" and "intelligent cruise control.
Autonomous cruise control is an optional cruise control system appearing on some more upscale vehicles. The system goes under many different trade names according to the manufacture. These systems use either a radar or laser setup allowing the vehicle to slow when approaching another vehicle and accelerate again to the preset speed when traffic allows. ACC technology is widely regarded as a key component of any future generations of smart cars.
Types
Laser-based systems are significantly lower in cost than radar-based systems; however, laser-based ACC systems do not detect and track vehicles well in adverse weather conditions nor do they track extremely dirty (non-reflective) vehicles very well. Laser-based sensors must be exposed, the sensor (a fairly-large black box) is typically found in the lower grille offset to one side of the vehicle.
Radar-based sensors can be hidden behind plastic fascias; however, the fascias may look different from a vehicle without the feature. For example, Mercedes packages the radar behind the upper grille in the center; however, the Mercedes grille on such applications contains a solid plastic panel in front of the radar with painted slats to simulate the slats on the rest of the grille.
Radar-based systems are available on many luxury cars as an option for approx. 1000-3000 USD/euro. Laser-based systems are available on some near luxury and luxury cars as an option for approx. 400-600 USD/euro.
Cooperating systems
Radar-based ACC often feature a Precrash system, which warns the driver and/or provides brake support if there is a high risk of a collision. Also in certain cars it is incorporated with a lane maintaining system which provides power steering assist to reduce steering input burden in corners when the cruise control system is activated.
Examples of vehicles with adaptive cruise control
2005 Acura RLAudi A4 (see a demonstration on YouTube), A5, A6, A8, Q7BMW 7 Series, 5 series, 6 series, 3 series (Active Cruise Control)2004 Cadillac DTS, STS, XLR2007 Chrysler 300C2006 Ford Mondeo, Taurus, S-Max, Galaxy2003 Honda Inspire Accord, LegendHyundai Genesis (Smart Cruise Control, delayed)Infiniti M, Q45,QX56, G35, FX35/45/50 and G371999 Jaguar XK-R, S-Type, XJ, XF2000 Lexus LS430/460 (laser and radar), RX (laser and radar), GS, IS, ES 350, and LX 570Lincoln MKS, MKT1998 Nissan Cima, Nissan Primera T-Spec Models (Intelligent Cruise Control)1998 Mercedes-Benz S-Class, E-Class, CLS-Class, SL-Class, CL-Class, M-Class, GL-Class, CLK-Class (Distronic, removed in 2009 from certain US models)Range Rover SportRenault Vel SatisSubaru Legacy & Outback Japan-spec called SI-Cruise1997 Toyota Celsior, Sienna (XLE Limited Edition), Avalon, Sequoia (Platinum Edition), Prius, AvensisVolkswagen Passat, Phaeton, Touareg, 2009 GolfVolvo S80, V70, XC70, XC60
ACTUATOR ( AS-i)
ACTUATOR ( AS-i)
In recent years, automation technology has migrated to new methods of transferring information. Increasingly, field-level devices such as sensors and actuators have internal intelligence capabilities and higher communication demands. The AS-i bus system provides the solution for a digital serial interface with a single unshielded two-wire cable which replaces traditional cable harness parallel wiring between masters and slaves.
AS-i technology is compatible with any fieldbus or device network. Low-cost gateways exist to use AS-i with CAN, PROFIBUS, Interbus, FIP, LON, RS-485 and RS-232.
The AS-i uses the Isolation Penetration Technology. The AS-i follows the ISO/OSI model to successfully implement the master/slave communication.
In recent years, automation technology has migrated to new methods of transferring information. Increasingly, field-level devices such as sensors and actuators have internal intelligence capabilities and higher communication demands. The AS-i bus system provides the solution for a digital serial interface with a single unshielded two-wire cable which replaces traditional cable harness parallel wiring between masters and slaves.
AS-i technology is compatible with any fieldbus or device network. Low-cost gateways exist to use AS-i with CAN, PROFIBUS, Interbus, FIP, LON, RS-485 and RS-232.
The AS-i uses the Isolation Penetration Technology. The AS-i follows the ISO/OSI model to successfully implement the master/slave communication.
64-Point FT Chip
64-Point FT Chip
A fixed-point 16-bit word-length 64-point FFT/IFFT processor developed primarily for the application in an OFDM based IEEE 802.11a wireless LAN base band processor. The 64-point FFT is realized by decomposing it in to a two dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplication compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift and add operation. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The core area of this chip is 6.8mm². The average dynamic power consumption is 41mW at 20Mhz operating frequency and 1.8Volt supply voltage. The processor completes one parallel-to-parallel 64-point FFT computation in 23 cycles; it can be used for any application that requires fast operation as well as low power consumption.
A fixed-point 16-bit word-length 64-point FFT/IFFT processor developed primarily for the application in an OFDM based IEEE 802.11a wireless LAN base band processor. The 64-point FFT is realized by decomposing it in to a two dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplication compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift and add operation. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The core area of this chip is 6.8mm². The average dynamic power consumption is 41mW at 20Mhz operating frequency and 1.8Volt supply voltage. The processor completes one parallel-to-parallel 64-point FFT computation in 23 cycles; it can be used for any application that requires fast operation as well as low power consumption.
Three-dimensional integrated circuit(3-D ICs)
Three-dimensional integrated circuit(3-D ICs)
In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip with two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.
3D ICs vs. 3D packaging
3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate with off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D package that an SoC bears to a circuit board.
In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip with two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.
3D ICs vs. 3D packaging
3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate with off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D package that an SoC bears to a circuit board.
Manufacturing technologies
As of 2008 there are four ways to build a 3D IC:
Monolithic – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring.
Wafer-on-Wafer – Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon vias” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad.
Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dies may be added to the stacks before dicing.
Die-on-Die – Electronic components are built on multiple dies, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding.
Benefits
3D ICs offer many significant benefits, including:
Footprint – More functionality fits into a small space. This extends Moore’s Law and enables a new generation of tiny but powerful devices.
Speed – The average wire length becomes much shorter. Because propagation delay is proportional to the square of the wire length, overall performance increases.
Power – Keeping a signal on-chip reduces its power consumption by ten to a hundred times. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.
Design – The vertical dimension adds a higher order of connectivity and opens a world of new design possibilities.
Heterogeneous integration – Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Even more interesting, components with completely incompatible manufacturing could be combined in a single device.
Circuit security - The stacked structure hinders attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.
Bandwidth - 3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor. Wide buses in turn alleviate the memory wall problem.
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