Thursday, August 27, 2009
Brain Computer Interface
BioChip
The development of biochips is a major thrust of the rapidly growing biotechnology industry, which encompasses a very diverse range of research efforts including genomics, proteomics, and pharmaceuticals, among other activities. Advances in these areas are giving scientists new methods for unraveling the complex biochemical processes occurring inside cells, with the larger goal of understanding and treating human diseases. At the same time, the semiconductor industry has been steadily perfecting the science of microminiaturization.The merging of these two fields in recent years has enabled biotechnologists to begin packing their traditionally bulky sensing tools into smaller and smaller spaces, onto so-called biochips. These chips are essentially miniaturized laboratories that can perform hundreds or thousands of simultaneous biochemical reactions. Biochips enable researchers to quickly screen large numbers of biological analytes for a variety of purposes, from disease diagnosis to detection of bioterrorism agents.
A biochip is a collection of miniaturized test sites (microarrays) arranged on a solid substrate that permits many tests to be performed at the same time in order to achieve higher output and speed. Biochips can also be used to perform techniques such as electrophoresis or PCR using microfluidics technology (Fan, 2009; Cady, 2009).
== History ==oxygen electrode, thereby relating oxygen levels to glucose concentration. This and similar biosensors became known as enzyme electrodes, and are still in use today.
In 1953, Watson and Crick announced their discovery of the now familiar double helix structure of DNA molecules and set the stage for genetics research that continues to the present day (Nelson, 2000).
The development of sequencing techniques in 1977 by Gilbert (Maxam, 1977) and Sanger (Sanger, 1977) (working separately) enabled researchers to directly read the genetic codes that provide instructions for protein synthesis. This research showed how hybridization of complementary single oligonucleotide strands could be used as a basis for DNA sensing. Two additional developments enabled the technology used in modern DNA-based biosensors. First, in 1983 Kary Mullis invented the polymerase chain reaction (PCR) technique (Nelson, 2000), a method for amplifying DNA concentrations. This discovery made possible the detection of extremely small quantities of DNA in samples. Second, in 1986 Hood and coworkers devised a method to label DNA molecules with fluorescent tags instead of radiolabels (Smith, 1986), thus enabling hybridization experiments to be observed optically.
BIT FOR INTELLIGENT SYSTEM DESIGN
Friday, August 14, 2009
Bolt terminologies and working
Introduction:
Bolts are the temporary fastening elements used for assembling of parts. There are 4 models of engines are producing. In these 4 models there are different application, about 40. Maximum torque of 120 Kg-m is required for torquing Main bearing cap bolts of 170 engine model and Connecting rod bolts, Cylinder head bolts, Damper and crank pulley, fly wheel etc. Conventional method of torquing the engine component bolts using manual torque wrench is more operator fatigue and precise control of applied torque is not possible. The difficulties involved in torquing for tightening engine component bolts are listed below.
No fool-proofing arrangementMeasurement of applied torque is not possibleConsuming more Torquing cycle time
Electric Nut Runner is newly emerged torque control fastener tightening tool that is usually powered by Electric power. Electric nut runner mainly consists of 3 components.
They are
1.Spindle
2.Controller
3.Cable
Spindle is equipped with brushless motor and it will tighten the bolt and the spindle is connected to the controller through a cable. Controller receives the feed back signal from the spindle and based on that signal it gives the controlling signal to the spindle. Cable is used to connect both the spindle and controller.
Objective
In the existing method, impact wrench and manual torque wrenches are using for torquing the Main Bearing cap bolts, Cylinder head bolts, Damper and crank pulley, Fly wheel and Fly wheel housing bolts in engine assembly line. In this existing method of bolts torquing cycle time is more and also precise control of torque is not possible.
The objective of proposed work is to study the process requirements and Torquing sequence, mounting height details for Main Bearing cap bolts, Cylinder head bolts, Damper and crank pulley, Fly wheel and Fly wheel housing bolts and propose the Electric Nut Runners spindle and Controller Specifications based on the studied process requirements and torquing sequence, mounting height details to the Manufacturer of Electric Nut Runners.
The Proposed work also includes Installation of 5 Electric Nut Runner in Main Bearing cap bolts, Cylinder head bolts, Damper and crank pulley, Fly wheel and Fly wheel housing stations and 10 pneumatic Nut runners at Selected points in Engine assembly line.
The proposed work also involves calculation of bolts torquing cycle time by Existing Manual Air guns and Pre-calibrated Torque wrench method and by using Proposed Electric and Pneumatic Nut runners Method and to determine how proposed methods are more economical compared to existing process.Finally we discuss here about the working of all the electrical nut runners, there procedure of operation, schematic diagram, and other supportive to nut runners lke PLC programming, Bosch programming.
Scope of the Work:
In six Engine assembly stages namely Main bearing cap bolts, Connecting rod bolts, Cylinder head bolts, Flywheel housing bolts, Flywheel bolts requires high torque with precise control (± 2%). In case of connecting rod bolts in addition to the above, the bolts are to be tightened i.e. “yield to torque”. In these cases number of bolts per engine assembly is ranging from 6 to 36 bolts. With the targeted increase in production levels to 1500 (during 2007-08) the present production practices need to be more reliable and free from operator dependencies.
With enhanced levels of production it is increasingly difficult and practically not possible to achieve a consistent torquing accuracy since the click-type torque wrenches used at present have an accuracy of +/-15%. In this industry, Present practice of pre-torquing using Pneumatic impact wrenches which is followed by manual torquing with pre-calibrated torque wrenches to ensure the final torque consumes lot of time, leave scope for improper torque application apart from need for extra operator to assist while tightening.
The objective of the company is to increase the capacity of the Assembly shop. Thus the primary option is to reduce the Torquing cycle time.Application of Electric and Pneumatic Nut Runners results in reduction in torquing cycle time required for the Assembling of Engine, thus solving the problem of the company.
Scope of project extends to the installation of the electrical nut runners, suitable for all the models, conducting trials to test the feasibility of the nut runners with all the models, check all the sequences, calibration of the nut runners, educating the supervisors, workers so the t they can easily use it.
Bolt Terminology
Helix: The curve formed on any cylinder by a straight line in a plane that is wrapped around the cylinder with a forward progression.
External thread: A thread on the outside of a member. An example is the thread of a bolt
Internal thread: A thread on the inside of a member. An example is the thread inside a nut.
Major diameter: The largest diameter of external or internal threads
Axis: The center line running lengthwise through a screw.
Crest: The surface of the thread corresponding to the major diameter of an external thread and the minor diameter of an internal thread.
Block Oriented Instrument Software Design
A new method for writing instrumentation software is proposed. It is based on the abstract description of the instrument operation and combines the advantages of a reconfigurable instrument and interchangeability of the instrumentation modules. The proposed test case is the implementation of a microwave network analyzer for nonlinear systems based on VISA and plug and play instrument drivers.
Modern Instruments or Instrumentation setups are likely to be built-up around generic hardware and custom software. The disadvantage is that the amount of software required to operate such a device is very high. An acceptable development time for a reasonably low number of software bugs can therefore only be obtained if the software is maximally reused from earlier developments. Most attempts used a two-step approach. In the first step transport interface between computer and instrument is abstracted. The first step in this approach has always been quite successful. The first transport abstraction stems from the IEEE-488 interface. Afterward SICL and VISA were developed to support multiple transport busses (IEEE-488, RS-232 and later Ethernet and IEE-1394). These methods use a file as the conceptual model for an instrument. The commands sent to the files are independent of the transmission medium, medium dependency is localized only in the initialization call. Most interfaces that can be used for instrumentation control are, hence, supported by these frameworks.
In the second step the instrumentation command is abstracted to empower interchangeability of similar pieces of instrumentation. For this, the situation always has been much less obvious. Only end-users have something to gain in instrument interchangeability. An abstract model to programming instrumentation setups is proposed which is easy and general enough to be used for complex setups.
INTELLIGENT SYSTEM DESIGN
The increasing complexity of microelectronic circuitry, as witnessed by multi-chip modules and system-on-a-chip and the rapid growth of manufacturing process automation require, that more effective and efficient testing and fault diagnosis techniques be developed to improve system reliability, reduce system downtime, and esemnhance productivity. As a design philosophy, built-in-test (BIT) is receiving increasing attention from the research community. This paper presents an overview of BIT search in several areas of industry, including semiconductor, manufacturing.
Wednesday, August 12, 2009
Biochip
The development of biochips is a major thrust of the rapidly growing biotechnology industry, which encompasses a very diverse range of research efforts including genomics, proteomics, and pharmaceuticals, among other activities. Advances in these areas are giving scientists new methods for unraveling the complex biochemical processes occurring inside cells, with the larger goal of understanding and treating human diseases. At the same time, the semiconductor industry has been steadily perfecting the science of microminiaturization. The merging of these two fields in recent years has enabled biotechnologists to begin packing their traditionally bulky sensing tools into smaller and smaller spaces, onto so-called biochips. These chips are essentially miniaturized laboratories that can perform hundreds or thousands of simultaneous biochemical reactions. Biochips enable researchers to quickly screen large numbers of biological analytes for a variety of purposes, from disease diagnosis to detection of bioterrorism agents.
A biochip is a collection of miniaturized test sites (microarrays) arranged on a solid substrate that permits many tests to be performed at the same time in order to achieve higher output and speed. Biochips can also be used to perform techniques such as electrophoresis or PCR using microfluidics technology (Fan, 2009; Cady, 2009).
== History ==oxygen electrode, thereby relating oxygen levels to glucose concentration. This and similar biosensors became known as enzyme electrodes, and are still in use today.
In 1953, Watson and Crick announced their discovery of the now familiar double helix structure of DNA molecules and set the stage for genetics research that continues to the present day (Nelson, 2000). The development of sequencing techniques in 1977 by Gilbert (Maxam, 1977) and Sanger (Sanger, 1977) (working separately) enabled researchers to directly read the genetic codes that provide instructions for protein synthesis. This research showed how hybridization of complementary single oligonucleotide strands could be used as a basis for DNA sensing. Two additional developments enabled the technology used in modern DNA-based biosensors. First, in 1983 Kary Mullis invented the polymerase chain reaction (PCR) technique (Nelson, 2000), a method for amplifying DNA concentrations. This discovery made possible the detection of extremely small quantities of DNA in samples. Second, in 1986 Hood and coworkers devised a method to label DNA molecules with fluorescent tags instead of radiolabels (Smith, 1986), thus enabling hybridization experiments to be observed optically.
Tuesday, August 11, 2009
Asynchronous circuit
An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer protocols. This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signals.
Theoretical foundations
Petri Nets are an attractive and powerful model for reasoning about asynchronous circuits. However Petri nets have been criticized by Carl Hewitt for their lack of physical realism (see Petri net#Subsequent models of concurrency). Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model and process calculi.
The term asynchronous logic is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model - which uses 'conventional' data processing elements with completion indicated by a locally generated delay model - to delay-insensitive design - where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger and slower than synchronous (or bundled data) implementations, but which are insensitive to layout and parametric variations and are thus "correct by design."
Benefits
Different classes of asynchronous circuitry offer different advantages. Below is a list of the advantages offered by Quasi Delay Insensitive Circuits, generally agreed to be the most "pure" form of asynchronous logic that retains computational universality. Less pure forms of asynchronous circuitry offer better performance at the cost of compromising one or more of these advantages:
* Robust handling of metastability of arbiters.* Early Completion of a circuit when it is known that the inputs which have not yet arrived are irrelevant.* Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gating in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, which can result in increased power consumption if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of high-K dielectrics).* Freedom from the ever-worsening difficulties of distributing a high-fanout, timing-sensitive clock signal.* Better modularity and composability.* Far fewer assumptions about the manufacturing process are required (most assumptions are timing assumptions).* Circuit speed is adapted on the fly to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.* Immunity to transistor-to-transistor variability in the manufacturing process, which is one of the most serious problems facing the semiconductor industry as dies shrink.* Less severe electromagnetic interference. Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.* In asynchronous circuits, local signaling eliminates the need for global synchronization which exploits some potential advantages in comparison with synchronous ones. They have shown potential specifications in low power consumption, design reuse, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations.
Disadvantages
* Increased Complexity* More Difficult to Design* the performance analysis of asynchronous circuits is a complicated problem
Applications
Asynchronous CPU
Asynchronous CPUs are one of several ideas for radically changing CPU design.
Unlike a conventional processor, a clockless processor (asynchronous CPU) has no central clock to coordinate the progress of data through the pipeline. Instead, stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing stage is complete. In this way, a central clock is unnecessary. It may actually be even easier to implement high performance devices in asynchronous, as opposed to clocked, logic:
* components can run at different speeds on an asynchronous CPU; all major components of a clocked CPU must remain synchronized with the central clock;* a traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. When an asynchronous CPU completes an operation more quickly than anticipated, the next stage can immediately begin processing the results, rather than waiting for synchronization with a central clock. An operation might finish faster than normal because of attributes of the data being processed (e.g., multiplication can be very fast when multiplying by 0 or 1, even when running code produced by a naive compiler), or because of the presence of a higher voltage or bus speed setting, or a lower ambient temperature, than 'normal' or expected.
Asynchronous logic proponents believe these capabilities would have these benefits:
* lower power dissipation for a given performance level, and* highest possible execution speeds.
The biggest disadvantage of the clockless CPU is that most CPU design tools assume a clocked CPU (i.e., a synchronous circuit). Many tools "enforce synchronous design practices". Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable problems. The group that designed the aforementioned AMULET, for example, developed a tool called LARD to cope with the complex design of AMULET3.
Despite the difficulty of doing so, numerous asynchronous CPUs have been built, including:
* the ORDVAC (?) and the (identical) ILLIAC I (1951), * the ILLIAC II (1962);* The Caltech Asynchronous Microprocessor, the world-first asynchronous microprocessor (1988);* the ARM-implementing AMULET (1993 and 2000);* the asynchronous implementation of MIPS R3000, dubbed MiniMIPS (1998);* the SEAforth multi-core processor (2008) from Charles H. Moore.
The ILLIAC II was the first completely asynchronous, speed independent processor design ever built; it was the most powerful computing machine known to man at the time.
DEC PDP-16 Register Transfer Modules (ca. 1973) allowed the experimenter to construct asynchronous, 16-bit processing elements. Delays for each module were fixed and based on the module's worst-case timing.
The Caltech Asynchronous Microprocessor (1988) was the first asynchronous microprocessor (1988). Caltech designed and manufactured the world's first fully Quasi Delay Insensitive processor. During demonstrations, the researchers amazed viewers by loading a simple program which ran in a tight loop, pulsing one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective "clock rate") naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen was poured on the chip, the instruction rate shot up with no additional intervention. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate -- again, with no additional configuration.
Applications and Layered architecture
AppleTalk Networking
Implementing file transfer, printer sharing, and mail service among Apple systems using the Local Talk interface built into Apple hardware, these were the main tasks of AppleTalk developed by Apple Computer. AppleTalk ports to other network media such as Ethernet with the aod of LocalTalk to Ethernet bridges or by Ethernet add-in boards for Apple machines. In addition to many third-party applications, internetwork routing, transaction and data stream service, naming service, and comprehensive file and print sharing are some of the provisions of this multi-layered protocol. With the introduction of AppleTalk Phase 2 in 1989, the addressing capability of AppleTalk networks were extended and thereby provided compliance with the IEEE 802 standard. Some other additions present in AppleTalk Phase 2 were the range of available network layer addresses and the use of the IEEE 802.2 Logical Link Control (LLC) protocol at the Data Link Layer.
AppleTalk is a proprietary suite of protocols developed by Apple Inc for networking computers. It was included in the original Macintosh (1984) and is now deprecated by Apple in favor of TCP/IP networking. AppleTalk's Datagram Delivery Protocol corresponds closely to the Network layer of the Open Systems Interconnection (OSI) communication model.
The AppleTalk design rigorously followed the OSI model of protocol layering. Unlike most of the early LAN systems, AppleTalk was not built using the archetypal Xerox XNS system. The intended target was not Ethernet, and it did not have 48-bit addresses to route. Nevertheless, many portions of the AppleTalk system have direct analogs in XNS.
One key differentiation for AppleTalk was it contained three protocols aimed at making the system completely self-configuring. The AppleTalk address resolution protocol (AARP) allowed AppleTalk hosts to automatically generate their own network addresses, and the Name Binding Protocol (NBP) was a dynamic Domain Name System (DNS) system, mapping network addresses to user-readable names. Although systems similar to AARP existed in other systems, Banyan VINES for instance, nothing like NBP has existed until recently.Both AARP and NBP had defined ways to allow "controller" devices to override the default mechanisms. The concept was to allow routers to provide the information or "hardwire" the system to known addresses and names. On larger networks where AARP could cause problems as new nodes searched for free addresses, the addition of a router could reduce "chattiness." Together AARP and NBP made AppleTalk an easy-to-use networking system. New machines were added to the network by plugging them and optionally giving them a name. The NBP lists were examined and displayed by a program known as the Chooser which would display a list of machines on the local network, divided into classes such as file-servers and printers.One problem for AppleTalk is it was intended to be part of a project known as Macintosh Office, which would consist of a host machine providing routing, printer sharing and file sharing. However this project was canceled in 1986. Despite this, the LaserWriter included built-in AppleTalk. Apple released a file and print server known as the AppleShare File and Print Servers.Today AppleTalk support is provided for backward compatibility in many products, but the default networking on the Mac is TCP/IP. Starting with Mac OS X v10.2, Bonjour (originally named Rendezvous) provides similar discovery and configuration services for TCP/IP-based networks. Bonjour is Apple's implementation of ZeroConf, which was written specifically to bring NBP's ease-of-use to the TCP/IP world.
AppleTalk Address Resolution Protocol
AARP resolves AppleTalk addresses to physical layer, usually MAC, addresses. It is functionally equivalent to ARP.
AARP is a fairly simple system. When powered on, an AppleTalk machine broadcasts an AARP probe packet asking for a network address, intending to hear back from controllers such as routers. If no address is provided, one is picked at random from the "base subnet", 0. It then broadcasts another packet saying "I am selecting this address", and then waits to see if anyone else on the network complains. If another machine has that address, it will pick another address, and keep trying until it finds a free one. On a network with many machines it may take several tries before a free address is found, so for performance purposes the successful address is "written down" in NVRAM and used as the default address in the future. This means that in most real-world setups where machines are added a few at a time, only one or two tries are needed before the address effectively become constant.
AppleTalk is Apple's design of a simple, inexpensive and flexible network for connecting computers, peripheral devices, and servers. AppleTalk's flexibility allows it to be used to connect peripherals such as the LaserWriter, or act as a stand-alone local-area network for up to 32 nodes, or form portions of a larger network by using bridges and gateway devices.
What is AppleTalk? At a purely physical level, AppleTalk is a network with a bus topology that uses a trunk cable between connection modules. Interfacing with the network is handled by the Serial Communications Control chip found in every Mac. Any device (computer, peripheral, etc.) attaches to a connection box via a short cable (called a drop cable), as shown in figure 1. This type of network is known as a multidrop line or a multipoint link. AppleTalk is capable of supporting up to 32 nodes (devices) per network and can transmit data at a rate of 230,400 bits per second. Nodes can be separated by a maximum cable length of 1000 feet.
AppleTalk, as specified by Apple, is wired using relatively inexpensive shielded, twisted-pair cable and Apple's connection boxes. One box is required per device; in the case of the Mac, the box plugs into the serial printer port in the back of the Mac using an attached drop cable. A trunk cable segment from one node on the network plugs into one port on the connection box, and another cable segment leading to the next node in the network plugs into the other port on the box.
One of the advantages of AppleTalk relates to the design of these connection boxes. The boxes are designed so that the continuity of the trunk cable and the network is maintained even if a device is disconnected from the network by unplugging it from the connection box. (Unplugging the trunk from the connection box does disrupt the integrity of the network, however.) The physical layout of an AppleTalk network can therefore be designed by locating the connection boxes where desired without worrying if a device will be initially connected to each one of the boxes. Additional devices can be added to the network at any time simply by plugging them into the boxes.
There are alternatives to using Apple's connection boxes. Farallon Computing markets their PhoneNET system, which fully supports the AppleTalk protocols. In the case of PhoneNET, the physical transmission medium is ordinary telephone wire, allowing the user to use the in-house telephone wiring for his network. PhoneNET uses the two of the unused wires found in a normal telephone installation, supporting both a telephone and a Mac connected to the same telephone wall box. In addition, PhoneNET links are capable of supporting 3000-foot distances between nodes. Farallon has a series of devices (repeaters, Star Controller) for extending the network.
With the recent announcement of DuPont's system for AppleTalk, users can also use fiber optic connections for an AppleTalk network. A concentrator is also available for constructing star networks. Two advantages of the fiber optics system are its immunity to EMI-RFI interference and improved data security; nodes may be a maximum of 4900 feet apart.
AppleTalk Protocols and the OSI Model
The Physical Layer has the responsibility of bit encoding/decoding, synchronization, signal transmission/ reception and carrier sensing. As mentioned previously, the Serial Communications Control chip in the Mac takes care of the AppleTalk port, which happens to be the printer port on current Macs. As long as connection modules conform to the signal descriptions of the Physical Layer, any transmission medium can be used for the actual network.
The AppleTalk Link Access Protocol (ALAP) must be common to all systems on the network bus and handles the node-to-node delivery of data between devices connected to a single AppleTalk network. ALAP determines when the bus is free, encapsulates the data in frames, sends its data, and recognizes when data should be received. ALAP is also responsible for assigning node numbers to each station on a network. The ALAP software assigns a random node number when the Mac is booted and keeps that number as long as it does not conflict with a previously assigned node number (if it does conflict, ALAP tries again).
The Link Access Protocol uses a method called CSMA/CA, or carrier-sense multiple access with collision avoidance, for access control. Carrier sense means that a sending node first listens to the network to hear if any other node is using the bus and defers to the ongoing transmission. Collision avoidance means that the protocol attempts to minimize collisions between transmitted data packets. In AppleTalk CSMA/CA, all transmitters wait until the bus is idle for a minimum time plus a random amount of added time before transmitting (or retransmitting after a collision).
While the ALAP protocol provides delivery of data over a single AppleTalk network, the Datagram Delivery Protocol (DDP) extends this mechanism to include a group of interconnected AppleTalk networks, known as an internet. An internet can be formed, for example, by using a bridge between two, or more, AppleTalk networks.
AppleTalk's address header (a part of each data packet) is used for identification of a process on the network and consists of a socket number, node number, and network number. A socket is a communication endpoint within a node on the network. Sockets belong to processes or functions that are implemented within software in the node. One Mac may have several AppleTalk connections open at one time, so the node number is not enough to identify a network address. In addition, node numbers are unique only within a single physical network, so DDP requires that each network be assigned a network number. The Datagram Delivery Protocol takes care of assigning socket numbers, as well as node numbers and network numbers, to provide a unique identification for every process occurring on the AppleTalk network.
As we move on to the Transport Layer, several protocols exist to add different types of functionality to the underlying services. The Routing Table Maintenance Protocol (RTMP) allows bridges and internet routers to dynamically discover routes to the different AppleTalk networks in an internet. The routing tables pair network numbers with the local node number of the bridge through which the shortest path to that net exists.
The AppleTalk Transaction Protocol, or ATP, is part of the Transport Layer and is responsible for controlling the transactions (flow of data) between requestor and responder sockets. This transaction-oriented protocol can be contrasted to other types of transport layers which support a two-way link between clients that can act as though they had an error-free hardwired link between them.
The basic function of the Name Binding Protocol (NBP) is the translation of a character string name into the internet address of the corresponding client. A key feature of the network is that most objects are accessible by name rather than by address (better for the user). NBP also introduces the concept of a zone, which is an arbitrary subset of networks in an internet where each network is in one and only one zone. The concept of zones is provided to assist the establishment of departmental or other user-understandable grouping of the entities of the internet. AppleTalk names consist of three fields: the object name (e.g., Dave), the type name (e.g., printer), and the zone name (e.g., Bldg. 1).
The Echo Protocol (EP) is a simple protocol that allows any node to send data to any other node on an AppleTalk internet and receive an echoed copy of that data in return. The Echo Protocol is mainly meant for network maintenance functions.
The specifications for the AppleTalk Data Stream Protocol (ADSP) have not yet been published (Inside AppleTalk, current version dated July 14, 1986). ADSP is designed to provide byte-stream data transmission in a full duplex mode between any two sockets on an AppleTalk internet. The Zone Information Protocol (ZIP) is used to maintain an internet-wide mapping of networks to zone names. Most of ZIP's services are transparent to the normal (non-bridge) node; the majority of ZIP is implemented in the bridges of an internet. ZIP is used by the Name Binding Protocol to determine which networks belong to a given zone.
In the Session Layer, the AppleTalk Session Protocol (ASP) is a general protocol designed to interact with ATP to provide for establishing, maintaining and closing sessions. Central to ASP is the concept of a session; two network entities, one in a workstations and the other in a server, can set up an ASP session between themselves (identified by a unique sessions identifier). ASP is an asymetric protocol in that the workstation initiates the session connection and issues sequences of commands, to which the server responds; the server may not send commands to the workstation.
The specifications for the AppleTalk Filing Protocol (AFP) have not been generally publicized. However, AFP has been finalized with the introduction of the AppleShare file server software from Apple, which uses AFP. AFP is a presentation layer protocol designed to control access to remote file systems
Amoeba Organization
Introducing the concept of AMOEBA ORGANIZATION based on adaptability, which is the key to business success of modern days; but many organizations are too rigidly organized to adapt to constant change & seize new opportunities. Modern day organizations are lengthening their life span by reshaping internal systems for flexibility, modernizing their cultures & monitoring the ever-changing environments in which they operate.
ADSL - Assymetric Digital Subscriber Line
Digital Subscriber Line (DSL) is a technology that brings high bandwidth information to homes and small businesses over the existing 2 wire copper telephone lines. Since DSL works on the existing telephone infrastructure, DSL systems are considered a key means of opening the bottleneck in the of the existing telephone network, as telephone companies seek cost-effective ways of providing much higher speed to their customers. DSL is a technology that assumes digital data does not require change into analog form and back. This gives it two main advantages. Digital data is transmitted to your computer directly as digital data, and this allows the phone company to use a much wider bandwidth for transmitting it to you, thereby giving the user a huge boost in bandwidth compared to analog modems. Not only that, but DSL uses the existing phone line and in most cases does not require an additional phone line. The digital signal can be separated or filtered, so that some of the bandwidth can be used to transmit an analog signal so that normal telephone calls can be made while a computer is connected to the internet. This gives "always-on" Internet access and does not tie up the phone line. No more busy signals, no more dropped connections, and no more waiting for someone in the household to get off the phone.
Because analog transmission only uses a small portion of the available amount of information that could be transmitted over copper wires, the maximum amount of data that you can receive using ordinary modems is about 56 Kbps (thousands of bits per second). With ISDN you can receive up to 128 Kbps. This shows that the ability of your computer to receive information is constrained by the fact that the telephone company filters information that arrives as digital data, puts it into analog form for your telephone line, and requires your modem to change it back into digital. In other words, the analog transmission between your home or business and the phone company is a bandwidth bottleneck. DSL however offers users a choice of speeds ranging from 144 Kbps to 1.5Mbps. This is 2.5 times to 25 times faster than a standard 56 Kbps dial-up modem. This digital service can be used to deliver bandwidth intensive applications like streaming audio/video, online games, application programs, telephone calling, video conferencing and other high-bandwidth services.
Registration, Admission and Status (RAS)
The RAS channel is an unreliable channel which is used to carry messages used in the gatekeeper discovery and endpoint registration processes which associate an endpoint's alias address with its call signalling channel transport address. H.225.0 recommends time-outs and retry counts for various messages as the the RAS messages are transmitted on an unreliable channel.[para] Once an endpoint or gatekeeper cannot respond to a request within the specified timeout, may use the Request in Progress (RIP) message to indicate that it is still dealing out the request. An endpoint or gatekeeper receiving the RIP resets its timeout timer and retry counter.
Registration, Admission and Status (RAS), defined in the ITU-T H.225.0/RAS, is the protocol between endpoints (terminals and gateways) and gatekeepers. The RAS is used to perform registration, admission control, bandwidth changes, status, and disengage procedures between endpoints and gatekeepers. An RAS channel is used to exchange RAS messages. This signaling channel is opened between an endpoint and a gatekeeper prior to the establishment of any other channels.
Registration, admission, and status (RAS) is a component of a network protocol that involves the addition of (or refusal to add) new authorized users, the admission of (or refusal to admit) authorized users based on available bandwidth, and the tracking of the status of all users. Formally, RAS is part of the H.225 protocol for H.323 communications networks, designed to support multimedia bandwidths. RAS is an important signaling component in networks using voice over IP (VoIP).
RAS messages are exchanged on a specific frequency called the RAS channel. The RAS channel is the first to be opened, and precedes any communications between endpoints and gatekeepers in the network. Signals in RAS can be categorized as (1) gatekeeper discovery requests and responses; (2) admission, registration, and unregistration messages and responses; (3) location requests and responses; (4) status requests and responses; and (5) bandwidth-control requests and responses.
Adaptive cruise control System
An automotive cruise control system that automatically slows down the car if it is moving too close to the vehicle in front of it. A radar or laser unit located behind the grille determines the speed and distance of the vehicle in front. When the distance is computed to be safe again, the system accelerates the car back to its last speed setting. Also called "active cruise control" and "intelligent cruise control.
Autonomous cruise control is an optional cruise control system appearing on some more upscale vehicles. The system goes under many different trade names according to the manufacture. These systems use either a radar or laser setup allowing the vehicle to slow when approaching another vehicle and accelerate again to the preset speed when traffic allows. ACC technology is widely regarded as a key component of any future generations of smart cars.
Types
Laser-based systems are significantly lower in cost than radar-based systems; however, laser-based ACC systems do not detect and track vehicles well in adverse weather conditions nor do they track extremely dirty (non-reflective) vehicles very well. Laser-based sensors must be exposed, the sensor (a fairly-large black box) is typically found in the lower grille offset to one side of the vehicle.
Radar-based sensors can be hidden behind plastic fascias; however, the fascias may look different from a vehicle without the feature. For example, Mercedes packages the radar behind the upper grille in the center; however, the Mercedes grille on such applications contains a solid plastic panel in front of the radar with painted slats to simulate the slats on the rest of the grille.
Radar-based systems are available on many luxury cars as an option for approx. 1000-3000 USD/euro. Laser-based systems are available on some near luxury and luxury cars as an option for approx. 400-600 USD/euro.
Cooperating systems
Radar-based ACC often feature a Precrash system, which warns the driver and/or provides brake support if there is a high risk of a collision. Also in certain cars it is incorporated with a lane maintaining system which provides power steering assist to reduce steering input burden in corners when the cruise control system is activated.
Examples of vehicles with adaptive cruise control
2005 Acura RLAudi A4 (see a demonstration on YouTube), A5, A6, A8, Q7BMW 7 Series, 5 series, 6 series, 3 series (Active Cruise Control)2004 Cadillac DTS, STS, XLR2007 Chrysler 300C2006 Ford Mondeo, Taurus, S-Max, Galaxy2003 Honda Inspire Accord, LegendHyundai Genesis (Smart Cruise Control, delayed)Infiniti M, Q45,QX56, G35, FX35/45/50 and G371999 Jaguar XK-R, S-Type, XJ, XF2000 Lexus LS430/460 (laser and radar), RX (laser and radar), GS, IS, ES 350, and LX 570Lincoln MKS, MKT1998 Nissan Cima, Nissan Primera T-Spec Models (Intelligent Cruise Control)1998 Mercedes-Benz S-Class, E-Class, CLS-Class, SL-Class, CL-Class, M-Class, GL-Class, CLK-Class (Distronic, removed in 2009 from certain US models)Range Rover SportRenault Vel SatisSubaru Legacy & Outback Japan-spec called SI-Cruise1997 Toyota Celsior, Sienna (XLE Limited Edition), Avalon, Sequoia (Platinum Edition), Prius, AvensisVolkswagen Passat, Phaeton, Touareg, 2009 GolfVolvo S80, V70, XC70, XC60
ACTUATOR ( AS-i)
In recent years, automation technology has migrated to new methods of transferring information. Increasingly, field-level devices such as sensors and actuators have internal intelligence capabilities and higher communication demands. The AS-i bus system provides the solution for a digital serial interface with a single unshielded two-wire cable which replaces traditional cable harness parallel wiring between masters and slaves.
AS-i technology is compatible with any fieldbus or device network. Low-cost gateways exist to use AS-i with CAN, PROFIBUS, Interbus, FIP, LON, RS-485 and RS-232.
The AS-i uses the Isolation Penetration Technology. The AS-i follows the ISO/OSI model to successfully implement the master/slave communication.
64-Point FT Chip
A fixed-point 16-bit word-length 64-point FFT/IFFT processor developed primarily for the application in an OFDM based IEEE 802.11a wireless LAN base band processor. The 64-point FFT is realized by decomposing it in to a two dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplication compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift and add operation. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The core area of this chip is 6.8mm². The average dynamic power consumption is 41mW at 20Mhz operating frequency and 1.8Volt supply voltage. The processor completes one parallel-to-parallel 64-point FFT computation in 23 cycles; it can be used for any application that requires fast operation as well as low power consumption.
Three-dimensional integrated circuit(3-D ICs)
In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip with two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.
3D ICs vs. 3D packaging
3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate with off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D package that an SoC bears to a circuit board.
Manufacturing technologies
As of 2008 there are four ways to build a 3D IC:
Monolithic – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring.
Wafer-on-Wafer – Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon vias” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad.
Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dies may be added to the stacks before dicing.
Die-on-Die – Electronic components are built on multiple dies, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding.
Benefits
3D ICs offer many significant benefits, including:
Footprint – More functionality fits into a small space. This extends Moore’s Law and enables a new generation of tiny but powerful devices.
Speed – The average wire length becomes much shorter. Because propagation delay is proportional to the square of the wire length, overall performance increases.
Power – Keeping a signal on-chip reduces its power consumption by ten to a hundred times. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.
Design – The vertical dimension adds a higher order of connectivity and opens a world of new design possibilities.
Heterogeneous integration – Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Even more interesting, components with completely incompatible manufacturing could be combined in a single device.
Circuit security - The stacked structure hinders attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.
Bandwidth - 3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor. Wide buses in turn alleviate the memory wall problem.